In electronic devices it is often necessary to provide a mechanism to implement a delay in time. For example, in an Application Specific Integrated Circuit (ASIC) within a network switch, it is often necessary for a process module on the ASIC to implement a delay in its processing operations. The process module may need to implement the delay for any number of reasons, such as to allow time for a different module to execute, to prevent over consumption of resources, or for any number of other reasons. The usefulness of adding delays in processing circuits is well known.
One mechanism for implementing a delay provides a free running counter. The counter is incremented after a defined period of time. When it is desired to institute a delay, a process may take the time period of the desired delay and divide it by the defined period of time to determine the number of counter increments, also referred to as ticks, that will occur in the defined time period. A timestamp may be created by adding the current value of the counter to the determined number of ticks. Upon every tick, the value of the counter may be compared to the value of the timestamp. Once they are equal, the desired delay has completed.
In some cases, it may be necessary to have more than one delay at a time. For example, there may be several process modules, each requiring a delay of a different period of time. An implementation for maintaining multiple delays may build on the mechanism described above. Just as above, for each desired delay, a timestamp may be computed. The timestamps may then be placed in an ordered list, from smallest to largest timestamp. Upon each increment of the counter, the timestamp at the head of the list may be compared to the counter, and if they are equal, the delay has completed. Because the timestamps are ordered, the next delay to complete will always be at the head of the list.